One of the common trends in the electronics industry is the miniaturization of electronic devices. This is especially true for electronic devices operated through the use of semiconductor microchips. Microchips are commonly viewed as the so-called “brains” of most electronic devices. In general, a microchip comprises a small silicon wafer upon which are built thousands of microscopic electronic devices that are integrally configured to form electronic circuits. The circuits are interconnected in a unique way to perform a desired function.
With the desire to decrease the size of electronic devices, it is also necessary to decrease the size of the microchip and electronic devices thereon. This movement has increased the number and complexity of circuits on a single microchip.
Conventionally, electronic devices are formed side-by-side in a single plane on a common substrate, such as a silicon wafer. This side-by-side positioning, however, uses a relatively large amount of surface area or so-called “real estate” on the substrate. As a result, larger substrates are required.
A recent trend is to vertically stack semiconductor devices on a single substrate. However, the stacking of semiconductor devices adds an additional degree of complexity to arranging the components of the semiconductor device. Furthermore, the processing conditions for fabrication of stacked or superimposed devices must be controlled so as not to damage components in underlying devices. In addition to stacking semiconductor devices, individual devices may be formed having high aspect ratios (i.e., the ratio of height to width). However, these high aspect ratios can increase the risk of the breakage of the device because of the limited surface area of the bond between the device to the substrate. Similarly, as the size of the devices decrease, interconnects, such as bit lines and word lines, may also need to decrease in size, e.g., width. In some cases, the size of the device may be so small that it becomes impractical, if not impossible, to form interconnects of the desired size on the device.
One common type of electronic device found on a microchip is a diode. A diode functions as a type of electrical gate or switch. An ideal diode will allow an electrical current to flow through the diode in one direction but will not allow the electrical current to flow through the diode in the opposite direction. In conventional diodes, however, a small amount of current flows in the opposite direction. This is referred to as current leakage.
Conventional diodes are typically formed from a silicon material that is modified through a doping process. Doping is a process in which ions are diffused or implanted within the silicon and then activated. There are two general types of dopants: P-type dopants and N-type dopants. P-type dopants produce positive charged holes. In contrast, N-type dopants produce extra electrons with negative charges. In general, a semiconductor diode is formed when a material doped with a P-type dopant is placed adjacent to a material with an N-type dopant.
Conventionally, diodes are configured by positioning the two opposing doped materials side-by-side on a microchip. This side-by-side positioning, however, uses a relatively large amount of surface area on a microchip. As a result, larger microchips are required.
Furthermore, for a diode to operate, each side of the diode must have an electrical connection that either brings electricity to or from the diode. The minimal size of each side of the diode is in part limited in that each side must be large enough to accommodate an electrical connection. Since conventional diodes have a side-by-side configuration with each side requiring a separate electrical connection, the ability to miniaturize such diodes is limited. In addition, the requirement of having side-by-side electrical connections on a single diode increases the size and complexity of the microchip.
In order to rectify some of these shortcomings, various attempts have been made to form a vertical diode structure. For example, U.S. patent application Ser. No. 12/434,212 (now U.S. Pat. No. 8,034,716) to Gonzalez et al. titled Method of Making Semiconductor Structures Including Vertical Diode Structures, hereinafter referred to as “Gonzalez” and the disclosure of which is incorporated herein in its entirety by reference, describes one method of making a vertical diode structure. However, such vertical diode structures are formed using a polysilicon material which has a poor Ior/Ioff performance due to the low carrier mobility through the polysilicon material. Current leaks may also form at a grain boundary of the polysilicon material, thus also decreasing the Ion/Ioff performance of the diode. The method of forming such vertical diodes, as described in Gonzalez, also does not provide an adequate means of forming an electrical contact for the diode when the diode is miniaturized, such as when the width of the diode is less than about 20 nm.
Accordingly, there is a need for a method of forming a vertical semiconductor device including a diode which provides high Ion/Ioff performance and provides for easy accessibility of an electrical contact, such as a conductive strap, to the diode. Additionally, there is a need for a method of forming such diodes as part of a semiconductor device wherein the diode may be formed over a first electronic device without damaging the first electronic device.